Verif star

Way back, in another place and in another time, our back end guru referred to verification engineers as “verif star”. But he explained it wasn’t a compliment: he swiftly moved his finger in the air to indicate the star he was referring to was “*”, as in “verif*”, the regular expression meaning “all of you who verify this chip”. We all thought this was much cooler than being called DV Engineers, or Verification Engineer, so we adopted this as our official job title: verif*

Seen by software developers as “the people who make sure the NAND gates are working”, and seen by the ASIC designers as “the people who share their files with other people”, we are the verif*.

In any case, this post has been sitting in my “Draft” folder since 2008, it is time I get it out before someone else does.

Chuck Norris ASIC Design and Verification Quotes

Please reply with your Chuck Norris ASIC Design/Verification Quotes.

Chuck Norris only needs a 1-bit logic vector to count to infinity.
Chuck Norris only needs one SystemVerilog construct: force.
Regressions always pass when Chuck Norris watches them.

Chuck Norris never uses the release statement.
Chuck Norris can solve conflicting constraints without rewriting them.
Chuck Norris does not use constraints, he beats variables into submission.

Send me more!

GNU Make poetry

I use GNU Make a lot. A while back I wrote this:

Three rules for a thousand Vera files
Seven for the Designers in the Valleys of Verilog
Nine for a dynamic Register Abstraction Layer
One for processing the output log
In the Compute Cloud where the CPUs lie.

One target to rule them all, One vpath to find them
One target to bring them all and in the makefile build them
In the land of GNU Make where the DAG shines.