Verilog exit code for simulation status
April 11, 2016 Leave a comment
In wrote this post in 2008. We are in 2016, and I decided to publish it,. since one of my favorite bug has been fixed.
Until recently, Verilog could not pass an exit code to the parent process when it ends. The
$finish function can accept one argument, but it is for printing simulation time, statistics and CPU time to the screen.
To quote the release notes:
Starting with the K-2015-09 release, simulation executable generated by VCS returns a non-zero value in case of fatals, errors and assertion failures.
Look up the
-exitstatus options in the manual.