SystemVerilog for Verification seminar

Today I attended a SystemVerilog for Verification seminar by XtremeEDA. This was a high quality presentation, with good slides (ie real code was on the slides and I like code since it’s what I do all day). It had been a while since I looked at SV in this amount of detail. I guess the last time was when I attended an SV presentation by Cliff Cummings, and before that it was when I looked at SuperLog presented by Simon Davidmann back when I worked at the Big Nerd Ranch.

There was about 40 people at the seminar, so I think it was well attended. There were questions about randomization and constraint solver, and so while I though those concepts were now well adopted and well known, it seems I was wrong. There were questions on controlling the randomness of simulations. I guess those concepts have not made it to CS and EE programs in universities, or some people are simply new to this and the seminar was the place to ask. There is a great book by Janick Bergeron on all of this, I highly recommend it.

I don’t want to describe how great SV is as a programming language, because frankly, you can all read about it everywhere on the internet. Personally, I like the asic-world website because it shows actual code. What I am mostly interested in is the features the language does not have, because it’s always those features that I ultimately miss. But here is the catch: I have not used SystemVerilog, only Vera! So there I go, I can’t even comment on features SV does not have, since I haven’t used it!

Nevertheless, I have 5 “directed” questions about SV:

  1. Does SystemVerilog have covariant return types?
  2. Does SystemVerilog have classes that I can use without declaring or creating an instance (in Vera I need to declare an instance, but I don’t need to create it)?
  3. Does SystemVerilog have exception handling (throw, try-catch-finally)?
  4. Does SystemVerilog have destructors (so I can deallocate stuff, or close some IO I created outside of SV)?
  5. Are the functional coverage results stored in an open format like MySQL (it’s MY data, not the vendor’s)?

An interesting feature (or anti-feature) I learned about was that tasks can include time consuming statements, but don’t return a value, while functions do return a value (including void), but cannot consume time. Strange. Why would SV make a distinction, since it is annoying to have to use a task to consume time and return a value through an argument passed as a reference: why not have functions that can consume time? Distinguishing between tasks and functions is so… verilog! Strange or annoying I don’t know.

The assertions, aka SVA, look highly useful. They remind me of regular expressions, and I think that’s what they are: an entire state machine described as a one-liner cryptic expression.

Lastly, there will be a seminar by Cadence and Mentor on OVM in Ottawa on March 6th, 2008, I hope I can attend.


2 Responses to SystemVerilog for Verification seminar

  1. Sean says:

    1. No – youre stuck with whatever was in the base
    2. no – you must construct with new()
    3. No
    4. No – garbage collection with reference counting; with no mechanism built in to track
    5. No – but there’s a group at accelera that’s working on this

    And the task v function distinction is VERY useful! It’s like a typed function. If I create a base class method that is a function then you cannot extend it and pass time in your derived class version. Where if I have a task defined in my base class then I’m telling you that you probably want to be passing time in this one. Vera lacks this distinction and it’s annoying. We end up using an _t naming convention to convey this information. But like any naming convention it is inconsistent an unenforced.

  2. sanket says:

    2. You can create a virtual class and use the methods and functions.

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