Venerable Verilog turns 30 this year, and here is my very short list of things that I wish were not stuck in the 80′s!
- Verilog cannot return a user defined exit status like normal programming languages (e.g. sys.exit(1))
- Verilog does not give to the users access to raw command line argument values (e.g. argv)
- Verilog does not have a singly rooted hierarchy (proof that it’s needed: VMM and UVM had to create a base class from which everything else inherits)
- Verilog modules do not have conditional IO ports (like a generate statement to select IO ports, or parametrized IO ports)
On the other hand, Verilog has evolved quite a bit in a lot of critical areas to design and verification, and I will not list them here as they are all over the internet, and there are excellent books out there (I really liked SystemVerilog for Verification by Chris Spear).
Verilog is a unique language, in the sense that when a problem that cannot be solved presents itself, Verilog gains new keywords and sometimes new syntax, while other programming languages gain a new library, or gain the ability to solve the problem (e.g. generics in Java). This makes Verilog, fascinating and complicated at the same time, with 250 keywords to memorize (and 73 built-in system functions)!
Before purists correct me, yes I know, I am lumping Verilog and SystemVerilog in the same boat here, forgive me!